FTQC bridge

Fault-tolerant architectures care about logical error rate and wall-clock cycle time, not only physical readout accuracy. ARCADE’s optional QEC stage is a bridge from classifier metrics to those systems quantities. It binds readout noise into stim circuits and reports logical error rate together with decoder-aware timing.

The mapping in one line

[ p_\mathrm{readout} = 1 - \mathrm{accuracy} ]

Shorter acquisition usually raises that readout error probability. The interesting engineering question is whether a faster physical readout, plus its decoder, still yields an acceptable logical error rate at a shorter wall-clock cycle.

Wall-clock cycle

[ t_\mathrm{cycle} \approx t_\mathrm{readout} + t_\mathrm{decode} + \cdots ]

Default decoders differ by code family. PyMatching is the default for surface codes. A sinter-internal path is the default for color codes. A belief-matching proxy is the default for bivariate bicycle experiments. Override them in YAML when your study needs a different pairing. Procedural details live in Enable QEC and FTQC curves.

What this stage is and is not

Is	Is not
A consequence layer on top of a fair readout bake-off	A full FTQC stack or magic-state factory design tool
Memory-experiment logical error and duration curves	A claim that zoo accuracy equals device Pauli noise
Timing that includes decoder latency	Guaranteed decoder performance on your FPGA

Use the bridge when you already trust a classifier ranking and want to ask whether this accuracy and duration pair survives under a surface-code memory experiment. For the YAML and API recipe, follow the how-to. For metric definitions, see Metrics.